Memory Hierarchy Model Validation
نویسندگان
چکیده
The memory hierarchy model is a powerful tool that can separate the stall time in a multi-level cache. However, since no tool currently exists that is able to compute this information, it is diicult to validate the model. In this respect, a processor simulator can help. With a simulator, we can directly observe the stall time due to cache misses, and thus obtain cpi 0. We succesfully validate the memory model with the aid of the simplescalar simulator. The predicted t2 and tm are within 10% of the values output by the simulator.
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